Memory integrated circuitry

ABSTRACT

Memory integrated circuitry includes an array of memory cells formed over a semiconductive substrate and occupying area thereover, at least some memory cells of the array being formed in lines of active area formed within the semiconductive substrate which are continuous between adjacent memory cells, said adjacent memory cells being isolated from one another relative to the continuous active area formed therebetween by a conductive line formed over said continuous active area between said adjacent memory cells. At least some adjacent lines of continuous active area within the array are isolated from one another by LOCOS field oxide formed therebetween. The respective area consumed by individual of said adjacent memory cells is ideally equal to less than 8F 2 , where “F” is no greater than 0.25 micron and is defined as equal to one-half of minimum pitch, with minimum pitch being defined as equal to the smallest distance of a line width plus width of a space immediately adjacent said line on one side of said line between said line and a next adjacent line in a repeated pattern within the array. The respective area is preferably no greater than about 7F 2 , and most preferably no greater than about 6F 2 .

TECHNICAL FIELD

[0001] This invention relates generally to formation of memoryintegrated circuitry.

BACKGROUND OF THE INVENTION

[0002] The reduction in memory cell and other circuit size required forhigh density dynamic random access memories (DRAMs) and other circuitryis a continuing goal in semiconductor fabrication. Implementing electriccircuits involves connecting isolated devices through specific electricpaths. When fabricating silicon and other material into integratedcircuits, it is necessary to isolate devices built into the substratefrom one another. Electrical isolation of devices as circuit densityincreases is a continuing challenge.

[0003] One method of isolating devices involves the formation of asemi-recessed or fully recessed oxide in the non-active (or field) areaof the substrate. These regions are typically termed as “field oxide”and are formed by LOCal Oxidation of exposed Silicon, commonly known asLOCOS. One approach in forming such oxide is to cover the active regionswith a layer of silicon nitride that prevents oxidation from occurringtherebeneath. A thin intervening layer of a sacrificial pad oxide isprovided intermediate the silicon substrate and nitride layer toalleviate stress and protect the substrate from damage during subsequentremoval of the nitride layer. The unmasked or exposed field regions ofthe substrate are then subjected to a wet (H₂O) oxidation, typically atatmospheric pressure and at temperatures of around 1000° C., for two tofour hours. This results in field oxide growth where there is no maskingnitride.

[0004] However at the edges of the nitride, some oxidant also diffuseslaterally. This causes the oxide to grow under and lift the nitrideedges. Because the shape of the oxide at the nitride edges is that of aslowly tapering oxide wedge that merges into another previously formedlayer of oxide, it has commonly been referred to as a “bird's beak”. Thebird's beak is a lateral extension or encroachment of the field oxideinto the active areas where the devices are formed. Although the lengthof the bird's beak depends upon a number of parameters, the length istypically from 0.05 micron—0.15 micron per side.

[0005] This thinner area of oxide resulting from the bird's beakprovides the disadvantage of not providing effective isolation in theseregions, and as well unnecessarily consumes precious real estate on thesemiconductor wafer. Further, as circuit density commonly referred to asdevice pitch falls below 1.0 micron, conventional LOCOS techniques beginto fail due to excessive encroachment of the oxide beneath the maskingstack. The closeness of the masking block stacks in such instances canresult in effective joining of adjacent bird's beaks, thus effectivelylifting the masking stacks and resulting in no masking effect to theoxidation. To prevent this, LOCOS active area masks typically need to bespaced further apart than the minimum capable photolithographic featuredimension where such falls below 0.3 micron, especially where2-dimensional encroachment occurs.

[0006] The problem is exemplified in FIG. 1. There illustrated is anarray 10 of staggered active area regions or islands 11, 12, 13 and 14of a dynamic random access memory array. The areas surrounding each ofthe subject islands would constitute LOCOS field oxide. Active areaislands 11 and 13 are formed along a line 15 along which a plurality ofDRAM cells are ultimately formed. Islands 12 and 14 form a part ofanother line along which DRAM cells of the array are formed. Dimension16 constitutes a separation distance between adjacent lines of activearea, whereas dimension 18 constitutes the separation distance betweenadjacent active areas in the same line.

[0007] Unfortunately, dimension 18 typically ends up being at least 1.5times as great as dimension 16 because of the bird's beak encroachmentin two directions. Specifically, the ends of the desired active areasare subjected to bird's beak oxide encroachment both from the ends ofthe desired active area regions as well as laterally from the sides ofsuch regions. However at the lateral edges of the particular active areamask not at an end, such as where the arrowhead of dimension 16 inregion 11 is shown contacting the active area edge, the field oxide maskis only exposed to one dimensional oxide encroachment, that being onlyfrom laterally outside. Accordingly, the degree of encroachment is notas great along the edges as at the ends of the active area masks.

[0008] The FIG. 1 illustrated layout is typically utilized to result inindividual memory cells throughout the array occupying area equal to8F². A folded bit line array architecture is also utilized to provideacceptable and superior signal-to-noise performance in conjunction withthe 8F² cell array.

[0009] LOCOS field oxide isolation is generally accepted within theindustry to fail when the minimum photolithographic feature dimensionfalls below 0.3 micron due to the above end-to-end encroachment. Thetypical alternate isolation technique in such instances is trenchisolation. For example, an article by Chatterjee et al. from the 1996Symposium On VLSI Technology Digest Of Technical Papers, at page 156,entitled, “A Shallow Trench Isolation Study For 0.25/0.18 Micron CMOSTechnologies and Beyond”, provides that “As high performance CMOStechnology is scaled down to the current 0.35-0.25 micron generation,shallow trench isolation (STI) becomes indispensable due to itsadvantages compared to the conventional LOCOS-type isolation, viz.smaller channel-width encroachment, better isolation/latch-upcharacteristics, planar topography, and smaller junction edgecapacitance.” [emphasis added] In STI, trenches are formed in thesemiconductive substrate and filled with oxide such that the LOCOSbird's beak is eliminated. Trench isolation does, however, have its ownother processing drawbacks.

SUMMARY

[0010] In one aspect, the invention provides memory integrated circuitryhaving at least some individual memory cell size of less than 8F², where“F” is defined as equal to one-half of minimum pitch, with minimum pitchbeing defined as equal to the smallest distance of a line width pluswidth of a space immediately adjacent said line on one side of said linebetween said line and a next adjacent line in a repeated pattern withinthe array. In one preferred implementation, adjacent memory cells areisolated from one another by field oxide where “F” is no greater than0.25 micron. In another aspect, at least some of those memory cells ofthe array are formed in lines of active area which are continuousbetween adjacent memory cells in the line, with said adjacent memorycells being isolated from one another by a conductive line over saidcontinuous active area between said adjacent memory cells. In yetanother aspect, the invention provides the memory circuitry in the formof DRAM having word lines and bit lines, with the bit lines preferablycomprising D and D* lines formed in a folded bit line architecturewithin the array.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0012]FIG. 1 is a top diagrammatic view of an active area layout of aportion of a prior art dynamic random access memory array.

[0013]FIG. 2 is a top diagrammatic partial view of a portion of an arrayand peripheral circuitry thereto of dynamic random access memorycircuitry in accordance with the invention.

[0014]FIG. 3 is a top diagrammatic partial view utilized in the FIG. 2array illustrating a preferred folded bit line architecture.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0016]FIG. 2 is a top view of a portion of a semiconductive substrate(such as monocrystalline silicon) illustrating memory integratedcircuitry 30 comprising an array area 32 of memory cells and peripheralcircuitry area 34. In the context of this document, the term“semiconductive substrate” is defined to mean any constructioncomprising semiconductive material, including, but not limited to, bulksemiconductive materials such as a semiconductive wafer (either alone orin assemblies comprising other materials thereon), and semiconductivematerial layers (either alone or in assemblies comprising othermaterials). The term “substrate” refers to any supporting structure,including, but not limited to, the semiconductive substrates describedabove.

[0017] An array of word lines 33 is formed over the substrate. An arrayof bit lines and capacitors (not shown in FIG. 2) are formed outwardlyof word lines 33. Continuous lines of active area 36 are formed withinthe silicon substrate beneath word lines 33. Continuous active areas 36are ideally formed in substantially straight lines throughout the array,run perpendicularly relative to word lines 33, and alternatingly extendto opposing peripheral circuitry areas, as shown. Channel stop implants(not shown) are also preferably provided between active area lines 36 tominimize cell to cell leakage.

[0018] Conductive isolation lines 38, extending substantially parallelwith word lines 33, run substantially perpendicular with and are formedover continuous active area lines 36. Isolation lines 38 serve toelectrically isolate immediately adjacent memory cells along a givencontinuous active area line within the array which do not share a commonbit contact from one another. Such lines are subjected to a suitablepotential, such as ground or a negative voltage, to effectively providesuch isolation function. Isolation lines 38 alternate throughout thearray between respective pairs of two adjacent word lines 33 betweenwhich bit contacts are formed. The illustrated word lines 33 andisolation lines 38 are ideally formed utilizing photolithography to haverespective conductive widths which are less than or equal to 0.25micron, and as well to preferably provide separation between theconductive areas of immediately adjacent lines at also less than orequal to 0.25 micron.

[0019] Further, preferably all of the continuous active area lineswithin the array are formed with and isolated from one another by LOCOSoxide regions 42 formed therebetween. Such are most preferably formedutilizing nitride LOCOS masking material provided by photolithographywhere the distance between immediately adjacent nitride masking blocksis less than or equal to 0.25 micron. The field oxide is also mostdesirably grown to be less than or equal to 2500 Angstroms thick tominimize bird's beak encroachment into each active area to less than orequal to 0.05 micron per side where device pitch (device width plus thespace between immediately adjacent devices) is 0.4 micron or less.

[0020] Circles 45, 49, 51, and 53 represent exemplary storage nodecontacts for DRAM capacitors formed along one continuous active arealine 36. Such are not shown in the adjacent continuous active arearegions for clarity in the drawings. Circles 60 and 47 represent bitline contacts. Bit line contact 60 is shared by the two DRAM cells whichutilize contacts 49 and 51 to connect active area with the respectivestorage nodes of the capacitors. Outline 62 represents that areaconsumed over the substrate by an exemplary individual memory cell ofthe DRAM array. Such is equal to about 3F×2F, or less, where “F” isdefined as equal to one-half of minimum pitch, with minimum pitch (i.e.,“P”) being defined as equal to the smallest distance of a line width(i.e., “W”) plus width of a space immediately adjacent said line on oneside of said line between said line and a next adjacent line in arepeated pattern within the array (i.e., “S”). Thus in the preferredimplementation, the consumed area of a given cell is no greater thanabout 6F², which is less than 8F². Alternately, but less preferred, theconsumed area is no greater than about 7F². Ideally, “F” is no greaterthan 0.25 micron. Utilization of continuous active area as describedabove facilitates limiting bird's beak encroachment to one dimension andfacilitates utilization of LOCOS isolation between active area lineswhere “F” falls below 0.3 micron. Accordingly at “F” equal to 0.25micron, the area consumed by most if not all individual memory cellswithin the array will be less than 0.5 micron², more preferably nogreater than 0.4375, micron², and most preferably no greater than 0.375micron².

[0021] The preferred embodiments of the invention are ideallyencompassed in a folded bit line array, such as shown in FIG. 3. Suchcomprises a plurality of sense amplifiers 3 having respective pairs oftrue “D” bit lines 5 and complement “D*” bit lines 5′ extending from oneside of the amplifiers. Memory cells are formed and the intersections ofbit lines 5 and wordlines 7, and of bit lines 5′ and word lines 7′.

[0022] U.S. patent application Ser. No. 08/530,661 listing Brent Keethand Pierre Fazan as inventors is incorporated by reference.

[0023] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. Memory integrated circuitry comprising: an array of memory cellsformed in lines over a semiconductive substrate and occupying areathereover, the respective area consumed by at least some individualmemory cells within the array being equal to less than 8F², where “F” isno greater than 0.25 micron and is defined as equal to one-half ofminimum pitch, with minimum pitch being defined as equal to the smallestdistance of a line width plus width of a space immediately adjacent saidline on one side of said line between said line and a next adjacent linein a repeated pattern within the array; and at least some of the minimumpitch adjacent lines of memory cells within the array being isolatedfrom one another by LOCOS field oxide formed therebetween.
 2. The memoryintegrated circuitry of claim 1 wherein the memory cells comprise DRAMcells.
 3. The memory integrated circuitry of claim 1 wherein individualof the lines of memory cells are substantially straight throughout thearray.
 4. The memory integrated circuitry of claim 1 wherein the LOCOSfield oxide between adjacent lines is less than or equal to 2500Angstroms thick.
 5. The memory integrated circuitry of claim 1 whereinsaid respective area consumed by at least some individual memory cellswithin the array is no greater than about 7F².
 6. The memory integratedcircuitry of claim 1 wherein said respective area consumed by at leastsome individual memory cells if within the array is no greater thanabout 6F².
 7. Memory integrated circuitry comprising: an array of memorycells formed over a semiconductive substrate and occupying areathereover, at least some memory cells of the array being formed in linesof active area formed within the semiconductive substrate which arecontinuous between adjacent memory cells, said adjacent memory cellsbeing isolated from one another relative to the continuous active areaformed therebetween by a conductive line formed over said continuousactive area between said adjacent memory cells; the respective areaconsumed by individual of said adjacent memory cells being equal to lessthan 8F², where “F” is no greater than 0.25 micron and is defined asequal to one-half of minimum pitch, with minimum pitch being defined asequal to the smallest distance of a line width plus width of a spaceimmediately adjacent said line on one side of said line between saidline and a next adjacent line in a repeated pattern within the array;and at least some of the minimum pitch adjacent lines of memory cellswithin the array being isolated from one another by LOCOS field oxideformed therebetween.
 8. The memory integrated circuitry of claim 7wherein individual of the lines of continuous active area aresubstantially straight throughout the array.
 9. The memory integratedcircuitry of claim 7 wherein the LOCOS field oxide between adjacentlines is less than or equal to 2500 Angstroms thick.
 10. The memoryintegrated circuitry of claim 7 wherein the memory cells comprise DRAMcells.
 11. The memory integrated circuitry of claim 7 wherein saidrespective area consumed by at least some individual memory cells withinthe array is no greater than about 7F².
 12. The memory integratedcircuitry of claim 7 wherein said respective area consumed by at leastsome individual memory cells within the array is no greater than about6F².
 13. Dynamic random access memory circuitry comprising: an array ofword lines and bit lines formed over a semiconductive substrate definingan array of DRAM cells occupying area over the semiconductive substrate,at least some DRAM cells of the array being formed in lines of activearea formed within the semiconductive substrate beneath the word linesand which are continuous between adjacent DRAM cells, said adjacent DRAMcells being isolated from one another relative to the continuous activearea formed therebetween by a conductive line formed over saidcontinuous active area between said adjacent DRAM cells; the respectivearea consumed by individual of said adjacent memory cells being equal toless than 8F², where “F” is no greater than 0.25 micron and is definedas equal to one-half of minimum pitch, with minimum pitch being definedas equal to the smallest distance of a line width plus width of a spaceimmediately adjacent said line on one side of said line between saidline and a next adjacent line in a repeated pattern within the array;and at least some of the minimum pitch adjacent lines of memory cellswithin the array being isolated from one another by LOCOS field oxideformed therebetween; and the bit lines comprise D and D* lines formed ina folded bit line architecture within the array.
 14. The memoryintegrated circuitry of claim 13 wherein individual of the lines ofcontinuous active area are substantially straight throughout the array.15. The memory integrated circuitry of claim 13 wherein the LOCOS fieldoxide between adjacent lines is less than or equal to 2500 Angstromsthick.
 16. The memory integrated circuitry of claim 13 wherein saidrespective area consumed by at least some individual memory cells withinthe array is no greater than about 7F².
 17. The memory integratedcircuitry of claim 13 wherein said respective area consumed by at leastsome individual memory cells within the array is no greater than about6F².
 18. Dynamic random access memory circuitry comprising: an array ofword lines and bit lines formed over a bulk silicon semiconductivesubstrate defining an array of DRAM cells occupying area over thesemiconductive substrate, the word lines and bit lines having respectiveconductive widths which are less than or equal to 0.25 micron, the DRAMcells within the array being formed in lines of active area formedwithin the silicon substrate beneath the word lines and which arecontinuous between adjacent DRAM cells, said adjacent DRAM cells beingisolated from one another relative to the continuous active area formedtherebetween by respective conductive lines formed over said continuousactive area between said adjacent DRAM cells; at least some adjacentlines of continuous active area within the array being isolated from oneanother by LOCOS field oxide formed therebetween, said LOCOS field oxidehaving a thickness of no greater than 2500 Angstroms; the respectivearea consumed by individual of said adjacent memory cells being equal toless than 0.5 micron²; and the bit lines comprise D and D* lines formedin a folded bit line architecture within the array.
 19. The memoryintegrated circuitry of claim 18 wherein individual of the lines ofcontinuous active area are substantially straight throughout the array.20. The memory integrated circuitry of claim 18 wherein said respectivearea consumed by at least some individual memory cells within the arrayis no greater than 0.4375 micron².
 21. The memory integrated circuitryof claim 18 wherein said respective area consumed by at least someindividual memory cells within the array is no greater than 0.375micron².
 22. Dynamic random access memory circuitry comprising: an arrayof word lines and bit lines formed over a semiconductive substratedefining an array of DRAM cells occupying area over the semiconductivesubstrate, at least some DRAM cells of the array being formed in linesof active area formed within the semiconductive substrate beneath theword lines and which are continuous between adjacent DRAM cells, saidadjacent DRAM cells being isolated from one another relative to thecontinuous active area formed therebetween by a conductive line formedover said continuous active area between said adjacent DRAM cells; therespective area consumed by individual of said adjacent memory cellsbeing equal to less than 8F², where “F” is defined as equal to one-halfof minimum pitch, with minimum pitch being defined as equal to thesmallest distance of a line width plus width of a space immediatelyadjacent said line on one side of said line between said line and a nextadjacent line in a repeated pattern within the array; and the bit linescomprise D and D* lines formed in a folded bit line architecture withinthe array.
 23. The memory integrated circuitry of claim 22 whereinindividual of the lines of continuous active area are substantiallystraight throughout the array.
 24. The memory integrated circuitry ofclaim 22 wherein F is no greater than 0.25 micron.
 25. The memoryintegrated circuitry of claim 22 wherein said respective area consumedby at least some individual memory cells within the array is no greaterthan about 7F².
 26. The memory integrated circuitry of claim 22 whereinsaid respective area consumed by at least some individual memory cellswithin the array is no greater than about 6F².